A 10-Gb/s 16:1 multiplexer and 10-GHz clock synthesizer in 0.25-/spl mu/m SiGe BiCMOS

A 10-Gb/s 16:1 multiplexer, 10-GHz clock generator phase-locked loop (PLL), and 6 /spl times/ 16 b input data buffer are integrated in a 0.25-/spl mu/m SiGe BiCMOS technology. The chip multiplexes 16 parallel input data streams each at 622 Mb/s into a 9.953-Gb/s serial output stream. The device also produces a 9.953-GHz output clock from a 622- or 155-MHz reference frequency. The on-board 10-GHz voltage-controlled oscillator (VCO) has a 10% tuning range allowing the chip to accommodate both the SONET/SDH data rate of 9.953 Gb/s and a forward error correction coding rate of 10.664 Gb/s. The 6 /spl times/ 16 b input data buffer accommodates /spl plusmn/2.4 ns of parallel input data phase drift at 622 Mb/s. A delay-locked loop (DLL) in the input data buffer allows the support of multiple input clocking modes. Using a clock generator PLL bandwidth of 6 MHz, the 9.953-GHz output clock exhibits a generated jitter of less than 0.05 UI/sub P-P/ over a 50-kHz to 80-MHz bandwidth and jitter peaking of less than 0.05 dB.