Improved Crossbar Array Architecture for Compensating Interconnection Resistance: Ferroelectric HZO-Based Synapse Case

In-memory computing is a promising solution to break through the conventional von Neumann bottleneck. Owing to the low-power consumption, Si fabrication compatibility and fast switching speed, the HfZrOx (HZO)-based ferroelectric devices attract attention as artificial synapses. By using crossbar architectures, artificial synapse array can greatly speed up the efficiency for neuromorphic applications. However, interconnect resistance effect will cause a serious decrease in calculation accuracy. This paper proposes a crossbar array architecture with the HZO-based ferroelectric synapses, which can restore the current distortion caused by the interconnect resistance. At the device level, the synaptic potentiation and depression behaviors are achieved by adjusting the pulse duration. For the circuit level, the interconnect resistance can be significantly compensated. In neuromorphic computing, a high accuracy rate of 96% is realized, which can be further improved with the expansion of the array size. Our results provide a step towards the development of large-scale ferroelectric HZO-based neuromorphic devices.