A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems

This article presents a pulse-amplitude modulation (PAM)-4-based 25.6-Gb/s serial interface for high-bandwidth (BW) and large-capacity storage systems consisting of NAND flash memory. A conventional interface with multi-drop bus topology between the NAND flash memories and their controller has an inevitable tradeoff between BW and capacity if we assume a reasonable PCB design in which the numbers of pins and wires near the NAND controller is limited. Although a daisy-chain-based interface can resolve this tradeoff, it requires the additional overheads of bridge chips and procedures for distinguishing between bridge chips. In order to address these challenges, this article presents three key techniques: 1) ring topology; 2) PAM-4-based four-channel multiplexing; and 3) cascaded clock and data recovery (CDR) circuits with phase-error-dependent bang-bang phase detector (PED-BBPD). The fabricated transceiver for the proposed interface using a 28-nm CMOS process achieves energy efficiency of 3.69 pJ/b at 25.6-Gb/s PRBS31 with a bit error rate (BER) of less than
$10^{-15}$
through a short channel with 1.84-dB loss. The proposed interface mitigates the overhead of the bridge chips with higher data rate than previous works, and it can achieve a state-of-the-art figure of merit of 1.80 PKG Gb/s/mW, defined as “No. of NAND packages (PKGs)
$\times $
data rate/power consumption,” with a controller and four bridge chips.