Design oriented analysis of package power distribution system considering target impedance for high performance microprocessors

This paper presents an efficient design methodology to realize the output impedance at the high performance microprocessor core equal to or less than the target impedance to reduce the mid-frequency core noise. Based on the frequency domain analysis of the lumped model of the package power distribution network (PPDN), a systematic method of estimating capacitance and associated parasitics of decoupling capacitors used in the distributed model of the PPDN is described. The simulation results of the analytical method show good correlation with the SPICE simulation results of the distributed PPDN model to reduce the output impedance at the core.