Global multi-level reduction technique for nonlinear simulation of high-speed interconnect circuits

Presents two approaches for simulation of large interconnect networks with linear/nonlinear terminations. The first approach is suitable in forming macromodels of interconnect networks in order to use them repeatedly in different configurations. The second approach is a nonlinear time-domain circuit reduction technique that reduces the whole interconnect network including the nonlinear/linear terminations. This method is independent of the number of ports in the system.