32 taps digitally controlled buffered potentiometer

The paper presents a 32-tap digitally controlled buffered potentiometer designed in a 0.8 /spl mu/m CMOS process. An up/down counter determines which tap is connected to the output. Output settings are stored in nonvolatile memory. A rail-to-rail op amp is used as unity-gain buffer at the output in order to eliminate the errors given by the load.