III-V material and device aspects for the monolithic integration of GaAs devices on Si using GaAs/Si low temperature wafer bonding

A new process for wafer scale integration of GaAs optoelectronic devices with Si integrated circuits has been investigated, based on low temperature bonding of epitaxial GaAs wafers onto planarized fully processed CMOS/BiCMOS wafers. The basic process flow and the most important aspects of the work concerning the III-V material and devices are presented.