40-Gbit/s D-type flip-flop and multiplexer circuits using InP HEMT

We developed a novel design technique for a D-type flip-flop (D-FF) circuit that is based on a small-signal-equivalent circuit approach. This technique provides the best condition to operate the D-FF at a high frequency. Using this technique, we fabricated a master-slave D-FF using a 0.15-/spl mu/m InP HEMT technology. We achieved 40-Gbit/s operation with clear-eye-waveform patterns and reduced jitter.