High-performance programmable SISO decoder VLSI implementation for decoding turbo codes

We developed a high-performance programmable SISO decoder LSI for decoding turbo codes based on the SW-log-BCJR algorithm. This LSI is based on the original architecture and memory management method, which guarantees the order of the soft-output to be the same as soft-input without attaching LIFO memory. Moreover, we propose new accurate implementation on 4-input log-sum operations used in the recursion of /spl alpha/ and /spl beta/ for codes of rate 2/3 and 3/3. This technique enables high operating frequency and low coding loss simultaneously. The interleaver and inevitable delay lines required to realize the turbo decoders are embedded on the chip so the most turbo code applications, including parallel concatenated convolutional codes (PCCC), serial concatenated convolutional codes (SCCC), turbo trellis coded modulation (TTCM) and serial concatenated trellis coded modulation (SCTCM), can easily be implemented scalably by cascading this LSI. The LSI is fully programmable for code types, code polynomials and interleaver patterns and applicable for BPSK, QPSK and 8-PSK with arbitrary signal constellation. An operating frequency of 100 MHz is achieved using CMOS 0.25 /spl mu/m process whereas the coding loss according to implementation is kept within 0.03 dB.