Addressable failure site test structures (AFS-TS) for CMOS processes: Design guidelines, fault simulation, and implementation

As technologies scale down, semiconductor manufacturing processes require more and more areas for test structures to ensure accurate yield estimation. This paper presents design guidelines for test structures with addressable failure sites to efficiently utilize a given area. Different types of test structures with three-level interconnects are developed and validated using a novel simulation system. Based on the proposed algorithm, single and multiple defects can be detected and identified precisely without ambiguity. The methodology standardizes the design of test structures for defect capturing as well as their usage within a common pad frame, which can be shared for various processes and applications. A test chip of 22/spl times/6.6 mm/sup 2/ containing a variety of types of these test structures was implemented to demonstrate the design feasibility.