Research on Flip-Chip Bonding Process and Thermal Cycle Reliability Simulation of 3-D Stacked Structure

In modern society, electronic equipment continues to develop in the direction of miniaturization and multifunction. In order to meet this requirement, packaging technology has gradually evolved from “2-D planar packaging” to “3-D packaging.” The realization of the flip-chip bonding process and the thermal cycle reliability of the 3-D stacked structure are discussed in this article. First, to stack three substrates and a small size chip together, the flip-chip bonding machine was used to vertically stack the chips in the $Z$ -direction. Then, the finite element software was used to analyze the thermal stress distribution of the overall structure under the thermal cycle load, and the life of the critical solder joints in the package was predicted. The simulation results show that, compared to the solder joints between the substrates, the copper pillar bumps of the small-size chip had a longer life.