Investigation of the degradation of InGaAs/InP double HBTs under reverse base-collector bias stress

In this paper, we report on the degradation of DC performance of InP/InGaAs/InP double heterojunction bipolar transistors (DHBTs) during electrical stress. Devices with different sizes were investigated under highly reverse base-collector (B-C) bias stress. The increase of B-C and emitter-base (E-B) junction leakage and decrease of current gain were observed. The increase of the junction leakage for both B-C and E-B junctions was found to scale with the junction perimeters which suggests that the stress-induced damages are localized at the junction peripheries. For the devices with larger emitter periphery-to-area ratio, a more pronounced decrease of current gain due to the stress was observed. The obtained experimental data indicate that the stress-induced degradation happens in high reverse B-C bias voltage (avalanche) regime. The degradation is believed to be induced by hot carriers rather than current. A physical model is proposed to explain the experimental observations.