Optimization of spin-on-glass process for multilevel metal interconnects

Spin-on-glass (SOG), an interlayer dielectric material applied in liquid form to fill narrow gaps in the sub-dielectric surface and thus conducive to planarization, is an alternative to silicon dioxide (SiO/sub 2/) deposited using CVD processes. The similar electrical properties between SOG and silicon dioxide guarantee that the SOG technique will provide comparable benefits to SiO/sub 2/ as an inter-metal dielectric layer. In fact, SOG has a lower dielectric constant and thus provides for better electrical insulation. However, its inability to adhere to metal and problems such as cracking prevent the easy application of SOG technology to provide an interlayer dielectric in multilevel metal interconnect circuits, particularly in university processing labs. This paper shows that a thin layer of CVD silicon dioxide and a curing temperature below the sintering temperature of the metal interconnect layer promotes adhesion, reduces gaps, and prevents cracking. Electron-scanning microscope analysis has been used to demonstrate the success of the improved technique. This optimized process has been used in three batches of double-polysilicon, double-metal CMOS wafers fabricated at the Microelectronics Research Center of Georgia Tech to date.