Bridging the gap between ISA compilers and silicon compilers: a challenge for future SoC design

Summary form only given. The emerging technology of the system-on-chip (SoC) is presenting new challenges at both the hardware and software stages of the design process. At present, system software engineers, e.g. high-level programming language (e.g. C/C++) compiler writers for processor cores, are working at the abstraction level of instruction set architecture (ISA) and its compiler optimization. On the other hand, the hardware engineers for the processor cores and other devices are working at a lower level abstraction level, e.g. RTL level, and using hardware description languages (e.g. VHDL, Verilog) and associated silicon compiler tools. Problems of communication gaps between the two world continue to exist due to the different abstraction levels, and the use of different design languages, incompatible tools and fragmented design flow, etc. The article discusses such gaps with examples illustrating the limits of optimization that can be performed from the hardware/software alone. With the demand for aggressive exploitation of instruction-level parallelism with high-performance uniprocessor cores, as well as the need for multiprocessor cores, such gaps must be bridged. Such optimization includes: instruction scheduling; register allocation, loop scheduling, locality optimization, etc. Such gaps also affect software debugging (including performance debugging) as well as hardware verification. We briefly outline solution challenges and opportunities in this direction.