Low-voltage low-power topology for high-speed applications

A low-voltage low-power logic architecture is introduced that uses capacitors to enhance high-frequency performance. A divide-by-32/33 BiCMOS dual-modulus frequency divider based on the proposed architecture operates at 2.5 GHz with a 3.15 mW power consumption from a 1.65 V power supply. Simulations show that, compared to conventional bipolar current-mode logic (CML) with the same supply current, the proposed architecture can operate at lower supply voltages.