On the design of modulo 2/sup n//spl plusmn/1 adders

In this paper we present new architectures for the design of modulo 2/sup n//spl plusmn/1 adders, which are based on the use of the same design block. Our design block incorporates a parallel-prefix carry computation unit with a carry increment stage. VLSI implementations of the proposed architectures in a static CMOS technology reveal their superiority against all already known architectures when the area * time/sup 2/ product is used as a metric and n > 8.