On-line calibration for non-linearity reduction of delay-locked delay-lines

A reduction of the non-linearity of a CMOS all-digital shunt-capacitor delay-line is achieved by performing an on-line statistical test of the line and correcting the individual cell delay mismatch according to the test results. A fully digital cell controller efficiently implementing the calibration procedure has been realized. Simulation results show the feasibility of the technique and the substantial reduction of the nonlinearity down to values lower then 1%.