Designing low-power energy recovery adders based on pass transistor logic

The novel design of various adiabatic adders based on pass transistor logic is introduced. Also, a new 1-bit full adder basic cell with a small number of transistors is designed. The architectural design of each adiabatic adder and new formulas for their corresponding delay, are presented. The performance of various adiabatic adders, in this work, against the performance of theirs CMOS counterparts, is discussed. All adders (i.e. conventional CMOS and adiabatic) were simulated by the PowerMill tool for power dissipation, latency and energy efficiency. In addition, a first estimation of area was done by the transistor count. Also all adders were simulated at 3.3 V and 5 V, for a broad range of frequencies. Experimental results indicate that the adiabatic adders outperform the corresponding conventional adders in terms of power consumption, and exhibit a lower hardware complexity.