Design of low-power domino circuits using multiple supply voltages

Dynamic logic circuits and especially the well studied domino CMOS circuits are favorable for implementing high-speed circuits. In the hope of reducing the power consumption besides achieving high speed, the effectiveness of applying the voltage scaling technique to the cell-based domino circuits is investigated in this work. A modified domino circuit with a contention-alleviated static keeper is proposed to improve the operating speed when the domino circuit is driven by a low-swing signal. A domino cell library and a cell-based design flow invoking the voltage scaling technique and the gate resizing technique have been developed. Experiments have been performed on the ISCAS'85 benchmark circuits, and the results show that almost 50% power reduction can be achieved even when the operating speed is kept unchanged.