A learning automata-based bus arbitration scheme for scalable shared-medium ATM switches

Shared medium ATM switches suffer from a major drawback: they are not scalable for large sizes, because they require a bus running N times faster than the ports (where N is the switch size, i.e. the number of input ports). Furthermore, ATM switches that are based on the TDMA bus arbitration scheme suffer from low performance when the offered traffic is bursty. In this paper a new approach to the design of scalable shared medium ATM switches, which overcome the above limitations, is introduced.