Towards a formal model of shared memory consistency for Intel Itanium/sup TM/

Provides a simple formal model for Itanium/sup TM/ shared memory consistency covering a core set of instructions, that is reverse-engineered from and . Our model sheds light on tricky concepts such as causality. It deals with cacheable memory instructions consisting of acquire loads, ordinary loads, release stores and ordinary stores, as well as memory fences. It does not currently handle atomic read-modify-writes, non-cacheable memory or special rules pertaining to data dependencies involving registers. Despite its simplicity, our model captures all published ordering properties of the instructions we consider. While operational models have been proposed for commercial shared memory systems (notably for Sparc V9), a notable feature of our operational model is its use of a few explicit devices such as vector timestamps to clearly describe the tricky notion of causality.