Noise-aware design for ESD reliability in mixed-signal integrated circuits

The design of electrostatic discharge (ESD) protection network in CMOS technology becomes increasingly more difficult because of shrinking device feature sizes, high operating speed, and system on a chip (SoC) environment. For SoC protection, many additional considerations are required such as complex power bus architecture, area overhead by protection circuits, and noise isolation during normal operations. We present a novel noise-aware design technique for superior noise margin and improved ESD reliability. The use of hierarchical electrostatic discharge (HED) provides a low impedance discharge path for any ESD event with smaller protection circuitry. The estimation of maximum power/ground voltage in digital circuits is helpful to determine an optimal topology of power clamp circuits subject to noise constraints. Experimental results demonstrate the effectiveness of this method.