Flexible IP blocks for customized synthesis

In order to leverage the optimality of custom design with the efficiencies of design synthesis and component reuse we present a new approach for IP blocks. A flexible architecture sized transistors block (FAST block) provides the means of locating an optimal architecture and transistor sizing scheme for the given synthesis constraints. In this paper we first introduce the FAST block methodology. We then present the foundation of a FAST block model for prefix adders. We follow with an example of the FAST block prefix adder model in action for various synthesis constraints.