A unified validation methodology for system level co-design and co-implementation

Describes a validation centric approach to the design architecting and implementation of System on Chip solutions. The proposed methodology allows an Integrator to rapidly utilise pre-defined IP objects consisting of both hardware, software and validation components which are structured in such as way as to minimise the effort in systems validation., Moreover the methodology tackles the issue of implementation certification once a suitable HW/SW partition has been selected. Current research using contemporary tool chains is used to illustrate the methodology.