Model reduction based on value dependency

Model checking is a fully automatic approach to verify large ASIC/SOC designs against their temporal specifications. However, its application is limited by the size of the system to be verified. Model reduction is one of the methods to tackle this problem. We propose a model reduction approach which is based on syntactic analysis of programs. The value domains of the state variables are extracted and analyzed based on the control flow diagram using a satisfiability (SAT) solver. The approach is sound based on the fact that the reduced system simulates the concrete system with respect to the properties. We also made a case study in the paper to show its performance.