A practical approach to DSM repeater insertion: satisfying delay constraints while minimizing area and power

Repeaters are now widely used to increase the performance of long on-chip interconnections in CMOS VLSI. Significantly high power consumption and area overhead due to optimal repeater insertion will soon be a bigger problem with the number of on-chip repeaters projecting to reach 700,000 in a 70 nm CMOS process. In this paper, we look at devising a methodology for minimizing power and area overhead of repeaters while meeting the target performance goals of on-chip interconnect lines. We integrate area and power overhead constraints along with delay into a repeater design methodology. We present a mathematical treatment for finding the number of repeaters and their sizes required for minimizing area and power overhead while meeting a given delay target. These expressions can easily be integrated into a repeater design methodology and CAD tool for interconnect planning. Our model is based on the Alpha-power law governing the MOSFET model to account for the short-channel effects and resistive loads that arise in deep sub-micron technologies. Results in 0.16 /spl mu/m, CMOS technology show that significant, reduction in area and power, of repeaters can be obtained by using the above design methodology.