Algorithm, architecture, and implementation of algorithmic delay-locked loop based data recovery circuit for high-speed serial data communication

An algorithmic delay-locked loop (DLL) based high-speed serial data recovery circuit (DRC) architecture is proposed. This scheme is based on a novel modulator-based phase synthesis and phase error compensation principle, which offers advantages of inherently instantaneous locking capability, high jitter tolerance, and unconditional loop stability. Its fully digital, highly regular, modular, and scaleable VLSI implementations is very suitable for the SoC solution to various high-speed, low power applications. The architecture has been implemented in test chips fabricated using a 0.25 /spl mu/m standard CMOS process technology. It occupied the area around 300 /spl mu/m /spl times/ 150 /spl mu/m, consumed less than 4 mW power. It demonstrated higher than 800 Mb/s data rate, and a better than 10/sup -9/ BER at 480 Mb/s rate and the best measured BER of better than 10/sup -12/ with a 2/sup 15/-1 pseudorandom data stream across a USB cable.