Vector Language: a proposed verification methodology for intellectual-property cores

When it comes to verifying Intellectual Property (IP) cores, there are no standard methodologies in existence today. The inconsistent use of many HDL language features has produced a wide array of techniques and ad hoc approaches. It is imperative to adopt a standard approach since approximately 70 percent of the design effort is dedicated to verification. A consistent and simple way of generating testbenches and test vectors for IP cores will reduce the verification's-learning curve and will allow the verification team, to concentrate on debugging the functionality of the design instead of debugging the testbench. This paper proposes a verification methodology for IP cores, using a simple and powerful Verilog coding style called Vector Language (VL). VL is a proven technique especially targeted for memory-mapped designs. It is easily portable from unit level to system level testbenches. It does not require special compilers and is compatible with every Verilog vendor, including Motorola's Stingray design system.