Performance evaluation of 3rd order sigma-delta (/spl Sigma/-/spl utri/) modulators via FPGA implementation

Sigma-delta (/spl Sigma/-/spl utri/) modulators have been widely used over the last few decades, in various signal processing applications. Usually, for improved signal-to-noise (quantization) performances, higher order modulators are utilized in these applications. In this paper, we investigate the performance of third order Sigma-delta (/spl Sigma/-/spl utri/) modulators and corresponding demodulators via Field Programmable Gate Array (FPGA) implementations. Two modulator architectures, the multi-stage (MASH) /spl Sigma/-/spl utri/ architecture and the Look Ahead Decision Feedback (LADF) /spl Sigma/-/spl utri/ architecture are compared on their performances. It is shown that the LADF /spl Sigma/-/spl utri/ architecture, which has not been widely reported in the literature, is preferable over the other modulators in the design of /spl Sigma/-/spl utri/ modulators. The selection of demodulator filters for reducing quantization noise resulting from the MASH and LADF /spl Sigma/-/spl utri/ architectures is also addressed in the paper. Advantages and disadvantages of various demodulator filters, e.g. sinc filters and recursive filters are discussed via the FPGA implementation.