Optimum halo structure for sub-0.1 /spl mu/m CMOSFETs

Optimized halo structures for sub-0.1 /spl mu/m CMOSFETs are evaluated. Halo profiling using indium implantation for nMOSFETs is investigated over a wide range of implantation dosages and energies. Performance degradation due to interstitial Si resulting from In-halo implantation can be reduced using thermal annealing at medium temperatures for longer periods of time. Lower-temperature composite liner-oxide/SiN-spacer technology is proposed for pMOSFETs to suppress device performance degradation. Optimized halo structures using indium for nMOSFETs and arsenic for pMOSFETs to obtain high-performance sub-0.1 /spl mu/m CMOSFETs are proposed.