Low-Power Compressor-Based Approximate Multipliers With Error Correcting Module

This letter proposes an unsigned approximate multiplier architecture segmented into three portions: the least significant portion that contributes least to the partial product (PP) is replaced with a new constant compensation term to improve hardware savings without sacrificing accuracy. The PPs in the middle portion are simplified using a new 4:2 approximate compressor, and the error due to approximation is compensated using a simple yet efficient error correction module. The most significant portion of the multiplier is implemented using exact logic as approximating it will results in a large error. Experimental results of 8-bit multiplier show that the power and power-delay products are reduced up to 47.7% and 55.2%, respectively, in comparison with the exact design and 36.9% and 39.5%, respectively, in comparison with the existing designs without significant compromise on accuracy.