A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-/spl mu/m CMOS/SIMOX ASICs

Silicon-on-insulator (SOI) devices have the great advantage of high operating speed in low supply voltages. This paper presents megabit-class high-speed and low-power embedded SRAM techniques for high data-throughput CMOS/SIMOX ASICs. In order to reduce the power dissipation of high-operating-frequency SRAMs, the multi-V/sub DD/ scheme using a low-voltage power supply only for restricted functional blocks is proposed along with the voltage-swing-matching circuit for "low-voltage" blocks. A squashed double-density layout of six-transistor-type memory cell realizes a small size of 8.64 /spl mu/m/sup 2/ under a 0.3-/spl mu/m CMOS/SMOX logic process including LOCOS isolation and plain local interconnections (e.g., tungsten-deposited diffusion layer and pseudocontacts). A new resistor-coupled current-sense amplifier makes it possible to detect the small readout signal from the memory cell with a short sensing time. To shorten the writing time, each bitline has an individual writing driver (per-bitline architecture). The recovery time of bitlines lowered to write data is also shortened with an accelerator combined with the pulse-reset wordline. A 64 K-words/spl times/16-bits SRAM test chip, fabricated with the 0.3-/spl mu/m pseudomulti-V/sub th/ CMOS/SIMOX process (a short gate length of 0.2 /spl mu/m is available for the fully depleted MOSFETs), has demonstrated the 300-MHz operation under a typical condition with 2- and 1-V power supplies. The power dissipation in standby is less than 0.1 mW and that at 200-MHz operation with a modified checkerboard test pattern is 35.6 mW for single fan-out loads.