Interconnection length estimation at logic-level

Accurate and fast interconnection length estimation of CMOS circuits during the design phase is essential to evaluate placement, routing and power estimation. The goal of this work is to estimate the average interconnection length of the nets for a given circuit at the logic level. We propose a look-up-table method, taking into account three parameters available at the logic level: number of cells, number of nets and fanout of each cell. To validate the method we use an automatic layout generator, TROPIC3, which generates the circuit layout from a SPICE netlist, reporting the net lengths after synthesis. The proposed method is compared with the values obtained after layout synthesis. The difference between estimated length and real length are lower then 10%.