A negative conductance voltage gain enhancement technique for low voltage high speed CMOS op amp design

A new circuit technique for voltage gain enhancement in CMOS op amp design suitable for low voltage and high speed operation is presented in this paper. A negative conductance is used to cancel the positive output conductance of an amplifier thereby reducing the total equivalent output conductance and increasing the voltage gain of the amplifier. The negative conductance is derived from the output conductance of a transistor, as opposed to a transconductance or some other parameters, to enhance tracking over process and environment variations. A single stage CMOS op amp was designed using this technique that achieved a simulated DC gain of 83 dB.