Evaluation of SMT decoupling design in a functioning high-speed PCB

SMT decoupling capacitor location in DC power bus design is a critical design choice. Experimental evaluation of SMT decoupling design is presented in this work for a functioning high-speed PCB transmitting 1.0625 Gb/s serial data. SMT decoupling capacitors were removed in several steps while the swept-frequency |S/sub 21/| and power bus noise were monitored. It was found that the SMT decoupling capacitors located in proximity to the test ports decreased |S/sub 21/| and power bus noise at high frequencies, even far above their series resonant frequency. The hardware measurements demonstrate that local decoupling can be beneficial for high-frequency noise mitigation.