A novel sub-50 nm poly-Si gate patterning technology

In this paper, a low-cost sub-50 nm poly-Si gate patterning technology is proposed and experimentally demonstrated The technology is optical resolution-independent, that is, it does not contain any critical photolithographic step. The masking layer for gate formation is from the pattern transfer of edge-defined spacer. Experimental results reveal that the resultant gate length is determined by the thickness of the film forming the spacer, and is about 75 to 85 percent of the deposited film thickness. SEM photographs show the cross-section of the poly Si gate fabricated using the proposed technology is an inverted-trapezoid, which can be utilized to reduce the gate resistance for transistor with the same gate length.