Statistical modeling of MOS devices based on parametric test data for improved IC manufacturing

In the manufacturing of VLSI circuits, engineering designs should take into consideration random variations arising from processing. In this paper, statistical modeling of MOS devices is reviewed, and effective and practical models are developed to predict the performance spread of MOS circuits due to the process variations. To illustrate their applications, the models are applied to a 0.25 /spl mu/m CMOS technology, and measured data are included in support of the model calculations.