Selectively clocked skewed logic (SCSL): a robust low-power logic style for high-performance applications

In very high performance designs, dynamic circuits, such as domino logic, are used because of their high speed. Skewed logic circuits can be used to achieve designs having performance comparable to that of domino but with better scalability. Moreover, a selective clocking scheme may be applied to enhance the power savings for skewed logic circuits. This paper proposes Selectively Clocked Skewed Logic (SCSL), a new circuit style based on skewed logic aiming for low clock power consumption. The results on ISCAS benchmark circuits implemented with this circuit design style show that the total power consumption can be reduced by 52.05% when compared to that of domino circuit with comparable performance.