Investigation of Endurance Behavior on HfZrO-Based Charge-Trapping FinFET Devices by Random Telegraph Noise and Subthreshold Swing Techniques

The HfZrO-based charge-trapping (CT) FinFET (CT-FinFET) devices with CT/de-trapping behavior occurring in the gate-stack provide a possible solution for embedded 1T DRAM application. In this brief, a novel method combining the random telegraph noise (RTN) and subthreshold swing (SS) is developed to investigate the endurance behavior of CT-FinFET devices, and the following advances have been achieved: 1) the traps in the gate-stack have been classified into two types: slow traps inside the HfZrO layer with deep energy level and fast traps at the interface with shallow energy level; 2) as the endurance cycles went on, the depth and energy level of slow traps increased, while the depth and energy level of fast traps kept the same, which indicated that the V
_th
shift is caused by the accumulation of holes' trapping in slow traps inside the HfZrO layer; 3) traps inside the HfZrO layer with deeper energy level and shallower depth can be easily occupied by holes during cycling; and 4) the generation of shallow-level traps at the interface contributes to the memory window (MW) degradation. This provides a useful tool for advancing the CT-FinFET technology.