Theoretical analysis and experimental characterization of the dummy-gated VDMOSFET

In this paper a novel silicon RF vertical double-diffusion metal-oxide-semiconductor field effect transistor (VD-MOSFET) structure with a dummy-gate incorporated between the active gates is proposed. The dummy-gate functions as a field plate to minimize the drain-to-gate feedback capacitance C/sub rss/ and also to raise the device breakdown voltage. Therefore, for the same blocking voltage rating, the dummy-gate structure allows the MOSFET to have a shorter channel and a larger gate to drain overlap area to minimize the on-state resistance. Hence, the transconductance gain G/sub m/ can be improved, leading to a higher RF performance for the power device. Experimental results show that with the dummy-gate a 51% lower on the feedback capacitance a 21% lower on the on-state resistance, a 100% increase in output resistance and a higher and linear transconductance are achieved. Furthermore, the safe operating area (SOA) of the device, which is limited by the turning-on of the parasitic transistor, is improved. This allows a higher power density to be handled by the proposed device.