50 nm MOSFET with electrically induced source/drain (S/D) extensions

A new bulk 50 nm metal oxide semiconductor field-effect transistor (MOSFET) with n/sup +/ poly-Si sidegates has been proposed and fabricated by using a mix-and-match technique. A main gate having a work function different from that of n/sup +/ poly-Si side-gates is adopted. In this work, p/sup +/ poly-Si is used for the main gate. Due to n/sup +/ floating sidegates (FSG) at both sides of the main gate, an inversion layer is induced under the FSG, which acts as an extended source/drain (S/D). Using 50 nm E-beam lithography and electron cyclotron resonance (ECR) N/sub 2/O radical oxidation for intergate oxide, the 50 nm NMOSFET was successfully fabricated. From the I-V characteristics, we obtained I/sub on/=690 /spl mu/A//spl mu/m at V/sub GS/-V/sub TH/=V/sub DS/=1.5 V for intrinsic 50 nm NMOSFET with 3 nm gate oxide. We investigated the effects of the FSGs on device characteristics and verified their reasonable operation. The coupling ratio of the main gate to the FSGs of the device was obtained to be about 0.75. We found the device has excellent short channel threshold voltage (V/sub TH/) roll-off characteristics due to an ultrashallow induced extended S/D. A scaling study shows that the proposed structure can be used even for 20 nm bulk MOSFETs.