Synthesis of a new manufacturable high-quality graded gate oxide for sub-0.2 /spl mu/m technologies

Graded gate oxide process involves a two-step synthesis of growing an oxide at a temperature above the viscoelastic temperature (T/sub VE/) onto a pregrown low temperature thermally grown SiO/sub 2/ layer to form a composite graded SiO/sub 2/ structure. The cooling rate is carefully modulated near T/sub VE//spl sim/925/spl deg/C to enhance growth induced stress relaxation. The pregrown SiO/sub 2/ layer provides grading and is a sink for stress accommodation for the final high temperature SiO/sub 2/ forming the interface. Both grading and modulated cooling generate a strain-free and planar Si/SiO/sub 2/ interface. Such an interface delivers significant enhancement in all aspects of device reliability and performance. These oxides are of very high-quality, robust, and manufacturable with a process capability index, C/sub pk/>1.5. Graded gate oxide is already in the primary path of our 0.16 /spl mu/m and 0.12 /spl mu/m technologies.