Dynamic and Steady State Response Analysis of Selective Harmonic Elimination in High Power Inverters

Selective harmonic elimination (SHE) technique has drawn tremendous interests for its superior harmonic performance, especially in high power devices where switching power loss and passive filter size are the main concerns. However, the drawbacks of slow dynamic response and difficulties in hardware implementation limit its engineering application. Based on a 3-level inverter, this paper analyzes the dynamic response of SHE. A system model is established and an improved method of updating the switching angles at sampling frequency is proposed. And a combination of notch filters and low-pass filter is designed to achieve a higher system bandwidth. The dynamic response and stability of the system are analyzed in detail. In addition, the influence of control errors on steady-state performance during hardware implementation is also discussed. A simple hardware structure of a DSP with a small-scale FPGA is adopted to realize the above method. Both dynamic response and steady-state response of the improved system are analyzed and compared with the regular SHE modulation and the widely used sinusoidal pulse width modulation (SPWM). Simulation and experimental results provided that the improved method proposed in this paper retains the excellent steady-state characteristics of the regular SHE modulation, and at the same time achieves as good dynamic performance as SPWM.