SSOI technology for integrated Schottky barrier diode

In fabricating MMICs on silicon, a conflict arises between the requirement of low resistivity silicon (LRS) for active device fabrication, and very high resistivity silicon (VHRS) for low interconnect loss. Two differing solutions are presented here. Low loss CPW lines have been fabricated on oxidised porous silicon (OPS) formed on 1-3 /spl Omega/cm silicon wafers, yielding typical losses of 8.5 dB/cm at 30 GHz. Alternatively, silicon on insulator (SOI) substrates, produced by bonding 1-3 /spl Omega/cm silicon wafers to 2-4 k/spl Omega/ "handle" wafers, give CPW line losses of 2.2 dB/cm at 30 GHz. In addition, by incorporating a buried tungsten layer to form a silicon-on-silicide-on-insulator (SSOI) structure, integrated Schottky barrier diodes, with low and controllable C/sub j/ and R/sub s/, can be produced.