Failure analysis from the back side of a die

Reproducible back side sample preparation and failure analysis methods becomes increasingly important due to the increasing number of metal levels within semiconductor devices and the ongoing transition to new packages like flip-chip or lead-on-chip. Defects are often located in the lowest chip levels, which make front side electrical defect localization very difficult. Otherwise electrical defect localization in flip-chip and lead-on-chip devices is only possible from the die back side. We developed a failure analysis flow for these die types which contains back side and front side failure analysis methods, consisting of back side photoemission microscopy after bulk Si thinning and electrical recontacting of the die for electrical defect localization. From the type of stress test, test results and fault location, the defect type can often be deduced. With junction leakage, latch up or Al spiking, the die should be prepared for front side analysis, since during further back side preparation, the whole die active area is removed. Gate oxide defects, particles and interrupted conductive interconnects can be analyzed from both the front and back sides of the die. Due to die fragility after bulk Si thinning for electrical defect localization, defect preparation becomes much easier from the back side. After bulk Si removal, optical inspection is possible. Particles or, for example, damage caused by electrostatic overstress might be visible. Gate oxide defects are analyzable by SEM and interrupted conductive interconnects are detectable using passive voltage contrast or electrical probing with AFM.