Low switching noise and load-adaptive output buffer design techniques

Switching noise due to di/dt is becoming severe as technology states, resulting in a great need for noise-suppression techniques. Several techniques to reduce the switching noise caused by output buffers in CMOS chips are described. An ac/dc output buffer design technique is proposed that includes an innovative feedback mechanism to reduce switching noise and output signal ringing while at the same time maintains timing and dc current requirement. Also, a technique of adaptively separated simultaneous switching noise is proposed that can increase the number of simultaneously switching outputs per V/sub DD/ and GND pair. Measurement results show that the ac/dc buffer can reduce the output ringing by 2.5/spl times/ and VDD/GND line bounce by 1.7/spl times/ and the ASN can double the number of simultaneous switching outputs under the same conditions as compared to the weighted and distributed buffer.