Design of the neural processor optimized for Xilinx Virtex FPGA devices

Focuses on the design of a parallel processor targeted at the rapid execution of neural networks. The basic architecture of the toroidal neural processor (TNP) is based on a toroidal mesh. This architecture was inspired by the need for a low-cost massively parallel processing system that could emulate a large variety of neural models. The TNP consists of two basic elements: a control unit and some processing units. The control unit acts as distributor of information and instructions for the processing units. The processing units perform exact operations on the data, based on the execution of instructions. The design of the TNP has a typical SIMD architecture. The processor has an enhanced interface with the host computer. This interface provides not only operations for programming and control of the TNP, but, in addition, any type of neural network and learning algorithm can be implemented through this interface. In the design of the TNP are implemented 10 control unit instructions and 11 processing unit instructions. The architecture of the TNP is optimized for Xilinx Virtex devices. The design uses many features of this family of FPGA devices. The VHDL constructs are mapped into hardware in the synthesis, optimization, place-and-route and implementation process. The optimization can significantly change the hardware that is generated. The TNP was tested, simulated and implemented in a Xilinx Foundation Technology Express version 3.3i environment with the Virtex XCV300 FPGA array and the HW-AFX-BG352-100 prototyping platform. The whole design can be implemented in Virtex E and Spartan devices too.