A Full-Duplex Receiver With True-Time-Delay Cancelers Based on Switched-Capacitor-Networks Operating Beyond the Delay–Bandwidth Limit

Wideband self-interference cancellation (SIC) in full-duplex (FD) radios requires the achievement of large delays to accurately emulate the SI channel. However, compact, power-efficient, low-loss/noise/distortion nanosecond-scale delays are extremely challenging to achieve on silicon. Passive transmission lines on silicon are lossy and area-intensive and exhibit reduced bandwidths when miniaturized using inductors and capacitors, whereas active approaches are noisy and power-hungry. In this work, we present a technique that leverages switched-capacitor circuits with multiphase clocking to obtain large on-chip delays over wide bandwidths with the low area and power consumption, thus exceeding the delay-bandwidth product (DBW) limits offered by conventional linear time-invariant (LTI) circuits. This technique is demonstrated in an FD receiver with time-interleaved switched-capacitor-based delay cells in RF and BB domains. The FD receiver is implemented in a standard 65-nm CMOS process and operates from 100 MHz-1 GHz with gain tunability of 15-38 dB, a noise figure of 5.4 dB, and power consumption of 31 mW. The RF/BB canceler delay cells have real-/complex-valued weighting with delays ranging from 0.2-1.1 ns/10-75 ns while consuming 25.5 and 6.5 mW, respectively. These large tunable delays perform FIR-filtering-based cancellation, enabling 30-35-dB integrated SI cancellation over 20 MHz on top of an off-the-shelf ferrite circulator when terminated by a dipole antenna (isolation of 22 dB), and can handle TX power of up to +9 dBm. Under SIC, the RF and BB cancelers degrade the RX noise figure by 1.1 and 0.8 dB, respectively.