An efficient self-test strategy for testing VLSI chips

The author describe a strategy for built-in self-test in conjunction with the boundary-scan technique applicable to VLSI chips. The method allows self-test features implemented at chip level to be transported into the field. As a result, the test effort for higher-level packages can be reduced. The test strategy is incorporated in an IBM/370 processor chip set. The hardware overhead (in circuits) needed for self-test is about 1.5% more than that for a normal level-sensitive scan-design implementation. Although most of this additional circuitry is provided as macros to logic designers, some extra design effort is needed for designing self-testable VLSI-components.<
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