Automatic generation of symbolic cells from a net-list description

A tool capable of synthesizing the symbolic layout of a CMOS cell from its circuit descriptions is presented. The synthesis process is guided by topological constraints on pin and transistor positions, maximum lengths of poly and diffusion wires, and the specification of a preferred layer for each electrical node. The optimization criteria, take into account cell area and aspect ratio, wire length, capacitance to the substrate, and contact and via minimization. The novel placement strategy includes transistor clustering into regions, global region placement by linear ordering, and two-dimensional local transistor placement. The routing combines Steiner trees and Lee algorithms. The program is fast and has been thoroughly tested on small and medium-sized cells.<
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